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Microelectronics

XDCHECK

Customer: X-FAB Semiconductor Foundries AG (Erfurt, Germany).
Platforms: MS Windows, Sun Solaris, Linux (console application).
Realization: C++ (MS VS, gcc, STL, Boost)
Functions: Checks Verilog netlists for design rule violations, prints statistical information.

More details

Selectively checks for following design rule violations:
    improper connections of cells or cell pins; missing or multiple signal holder cells; max fanout limit exceeded; combinatorial loops, long nets; gated Clock, Set or Reset signals; unsynchronized primary input signals
  • improper connections of cells or cell pins;
  • short-circuited bistable gate pins;
  • improper tristable gate connection(permanently turned on/off enabling inputs, short-circuited enabling inputs of different gates, circuits with single tristable outputs);
  • Set or Reset memory cell input manipulation with the same signal or with its own signal through combinatorial gates;
  • memory cell pins connection to data inputs without Set or Reset;
  • missing or redundant level-support cells;
  • output-input combinatorial gate connection of one or two gates;
  • feedback loops;
  • combinatorial loops, long nets;
  • max fanout limit exceeded;
  • improper cell to pad connection;
  • synchronization and reset circuits connected to combinatorial gates;
  • unsynchronized input circuits.
Statistics:
  • gate count;
  • total cell area;
  • pin list;
  • Clock, Set and Reset nets and trees;
  • design hierarchy;
  • max fanout per net.

XECHECK

Customer: X-FAB Semiconductor Foundries AG (Erfurt, Germany).
Platforms: MS Windows, Sun Solaris, Linux (console application).
Realization: C++ (MS VS, gcc, STL, Boost)
Functions: Compares semantics of two Verilog netlists; checks permission for found differences. Differences are derived with the use of discrepancy discription language. Permitted differences are stored in an alert file, forbidden - in an error file.

More details

Permitted differences could be described by designer or may correspond to some optimization procedures such as:
  • cell pin reordering;
  • changing of cell driving capability;
  • buffers insertion;
  • clock tree or set-reset tree insertion;
  • scan insert and reordering.

XLICDSM

Customer: X-FAB Semiconductor Foundries AG (Erfurt, Germany).
Platforms: MS Windows, Sun Solaris, Linux (console application).
Realization: C++ (MS VS, gcc, STL, Boost), Perl, XML, XSLT, CORBA.
Functions: standard cell library characterization

More details

Program performs timing, power and derating characterization of standard and IO cell libraries on heterogeneous platform (Windows, Solaris, Linux simultaneously) and with optional simulators(Synopsys HSPICE or Cadence SPECTRE). Characterization system includes two program modules:
  • characterization manager: reads information in XML database, prepares data for Synopsys HSPICE or Cadence SPECTRE simulation, sends tasks to simulation agents, receives and processes simulation results, saves them in XML database, exports library descriptions to target CAD systems (Verilog *.v, Synopsys *.lib etc.) and documentation (*.html).
  • remote simulation agents: receive tasks from characterization manager, launch simulator with received task on its own computer, send simulation results to characterization manager.
Perl and XSLT are extensively used for description of characterization methods and output templates. Data is stored in a XML database. Characterization manager and remote simulation agents interact with each other using CORBA protocol.

AMC

Customer: "PKK Milandr" (Moscow, Russia).
Platform: Linux (GUI/console).
Realization: C++ (MS VS, gcc, STL), XML, QT.
Functions: SPRAM memory compiler

More details

The SPRAM compiler enables automatic generation of single port RAM blocks for the 0.18 m CMOS process with configurations from 64 bit to 512 Kb. Compiler generates both back-end and front-end files: GDSII layout, LEF, CDL netlist, EDIF symbol, Verilog model, Cadence TLF, ASCII data table for desired configuration. SPRAM configurations are strictly characterized to provide timing and power parameters database which is used for generation of front-end files. UI enables configuration selection and front-end parameters preview.



.29 May
2009
01

The first iteration of the project STS-30 has been finished.
Details

.02 March
2007
02

Now everyone can create his own RBS-documents. Our program RBS-Transformer converts a set of HTML-files into single-file RBS-format.
Details

.25 January
2007
03

REBUS 1.1.9 is available for download.
Details

.29 December
2006
04

REBUS 1.1.8 - new release of the program.
Details

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