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Charisma is designed for automatic standard cell and i/o cell libraries characterization with the use of the external circuit simulation software. As an output Charisma generates cell's models in standard CAD formats necessary for chip design.

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Download the trial version of Charisma

Order libraries characterization

  • Most modern VLSI designs are based on standard cell libraries. Utilization of libraries for automatic development and verification is only possible under the condition of full and precise cell characterization. Characterization procedure is an integral part of sandard cell library development.
  • Charisma is a fully automated solution for standard cell library characterization with table models which have sufficient precision for manufacturing processes with channel length of 90 um or less.
  • While performing characterization Charisma generates tasks for external circuit simulation software (Hspice, Spectre, etc.) based upon settings and analysis of input descriptions of cells, distributes tasks among LAN processores, accumulates simulation results in a database and forms output files (.lib, .v) and documentation (.html, .pdf).
  • Charisma is a fast, accurate and easy-to-use automated solution for standard cell library characterization with affordable cost for chip manufacturers and standard and i/o cell library developers.

    Product users: JSC Micron (Moscow, Russia), RIMS (Nizhny Novgorod, Russia). Library characterization customers: IPMCE RAS (Moscow), SKTBES (Voronezh).

Types of characterized cells

  • combinatorial with one or several outputs
  • tristable
  • multiplexers
  • adders and half-adders
  • FF and latches (with set, reset, permission, scan-inputs)
  • special (with weak feedback, clock buffer, etc.)
  • input, output, bidirectional
  • tristable
  • with Schmitt trigger for input
  • with step-up/step-down input load
  • with open drain/source on the output
  • with several source voltages

Characterized paramaters

  • Time parameters:
    - propagation delay
    - output signal switch-over time
    - setting and holding times for a data signal
    - setting and holding times for setup and reset signals
    - minimal pulse width
  • Power parameters:
    - dynamic input and output power
    - static power
  • DC parameters:
    - input and output data level voltage
    - input level hysteresis
    - input and third state leakage current
  • Noise parameters:
    - voltage-current characteristi 
    - noise propogation
    - noise tolerance
  • Effective input capacitance
  • Paramaters dependency on conditions (process, voltage, temperature)

Output formats


  • Synopsys Liberty (.lib)
  • Verilog (.v)
  • hypertext (.html)
  • document (.pdf)

External circuit simulation software

  • Cadence Spectre
  • Synopsys Hspice
  • Unique IC's AVOSpice


  • Linux (Red Hat, Fedora core)
  • MS Windows
  • Sun Solaris
  • combined


  • Charisma-Base (standard cells, time and power parameters)
  • Charisma-Std (standard and input/output cells, time and power parameters, 5 licenses for parallel simulations)
  • Charisma-Prof (standard and input/output cells, time, power and noise parameters, 10 licenses for parallel simulations)
  • Additional options
  • Trial characterization  

System properties

  • Cell characterization for all possible in-out paths and input combinations
  • Automated input stimuli generation for combinatorial and sequential cells
  • Automated point of characterization selection «input front - output load»
  • GUI with library characterization status imaging in real time
  • Adjustable PVT-angle characterization parameters
  • Re-characterization of separate angles and cells option
  • Reduced simulation runs optimization
  • Output file size optimization
  • Export to output formats with given accuracy
  • Distributed simulation on unlimited CPUs (CPU cores)
  • Simulation resource management scheduler

Efficiency parameters

Average time of characterization of time and power parameters of 1 cell for 1 angle given 5 CPUs for simulation:

  • 0.35 um library (simulation step 0.01 ns, front/load table 44) — 15 min.
  • 0.18 um library (simulation step 0.001 ns, front/load table 77) — 2 hours. 
Linear dependancy of speed of characterization on number of CPUs (CPU cores) used for circuit simulation.

.29 May

The first iteration of the project STS-30 has been finished.

.02 March

Now everyone can create his own RBS-documents. Our program RBS-Transformer converts a set of HTML-files into single-file RBS-format.

.25 January

REBUS 1.1.9 is available for download.

.29 December

REBUS 1.1.8 - new release of the program.

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